In an Out-Of-Order (“OOO”) microprocessor, instructions are allowed to issue and execute out of their program order. The scheduler of an OOO microprocessor selects and dispatches ready instructions out of order into execution units. Certain microprocessor architectures have two types of instructions, A and E. Examples of A-type instruction are integer operations such as add and subtract while examples of E-type instructions are floating point operations such as floating point add, floating point subtract, and floating point multiply. However, it should be noted that A and E-type of instructions are not solely limited to the above examples.
Conventional architectures that support two types of instructions, however, do not have execution units that can support both types of instructions. For example, a conventional processor will typically have an exclusive execution unit for executing A-type instructions and an exclusive unit for processing E-type instructions, wherein both types of execution units would be mutually exclusive from each other.
The objective of the scheduler in such an architecture is typically to optimize the dispatch throughput given the non-uniform instruction type and the asymmetric execution units. Further, another objective of the scheduler is to prioritize older instructions over younger ones. And finally, the last objective is to maintain competitive latency in performing the scheduling procedure.
Conventional architectures are limited because they do not successfully accomplish all the aforementioned objectives. For example, as mentioned above, conventional architectures may adopt a primitive policy of selecting A-type instructions for execution in only A-type execution units and picking E-type instructions for execution in only E-type execution units. This allows execution to be conducted in parallel for better latency, but if there are not enough instruction blocks for the specific execution unit types, it will result in unused execution unit ports and less overall dispatch throughput.
For example, if there are 5 A-type instructions and 3 E-type instructions in an architecture with 4 A-type execution units and 4 E-type execution units, at least one of the E-type execution units will be idle because A-type instructions cannot be executed in E-type execution units. Another problem with this scheme is that it is age optimized only within the individual category (A or E) and not optimized for overall age prioritization. In the example above, for instance, only 7 instructions would be dispatched. The fifth A-type instruction would have to wait for the next cycle. As a result, conventional architectures are limited and not designed to accomplish all the aforementioned desired objectives of the scheduler.